Design and Simulation of Floating Point Multiplier Based on VHDL
نویسنده
چکیده
Multiplying floating point numbers is a critical requirement for DSP applications involving large dynamic range. This paper focuses only on single precision normalized binary interchange format targeted for Xilinx Spartan-3 FPGA based on VHDL. The multiplier was verified against Xilinx floating point multiplier core. It handles the overflow and underflow cases. Rounding is not implemented to give more precision when using the multiplier in a Multiply and Accumulate (MAC) unit.
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تاریخ انتشار 2013